The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventor(s), to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
The speed at which memory is accessed by, for example, system-on-chip (SOC) devices (e.g. in server computers or mobile telephones) has rapidly increased in recent years. In particular, double-data-rate (DDR) memory is a type of very fast computer memory that uses clock signals in a manner that allows twice the data to be transferred in the same amount of time. As the speed of memory access has increased, performance (e.g., data throughput) has increased. Furthermore, in some configurations, electrical power consumption has increased with the speed of memory access.
Today, more and more SOC applications demand a memory system having a more efficient balance between performance and power consumption. For example, certain SOC configurations demand a 32-bit double data rate 3 (DDR3) interface for high performance and also demand low power consumption for some lower performance modes of operation (e.g., 16-bit DDR3). In a configuration having two 16-bit DDR devices, one of the two devices may be powered down in a low performance/low power consumption mode of operation. However, in such a configuration, transitioning back to a high performance/high power consumption mode of operation, where both 16-bit DDR devices are powered up, typically includes having to remap regions of memory and/or reboot the SOC device. Such remapping and/or rebooting results in inefficient operation of the SOC device.